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| mosel vitelic 1 V54C316162VC 200/183/166/143 mhz 3.3 volt, 2k refresh ultra high performance 1m x 16 sdram 2 banks x 512kbit x 16 V54C316162VC rev. 1.4 december 2001 V54C316162VC -5 -55 -6 -7 unit clock frequency (t ck ) 200 183 166 143 mhz latency 3333clocks cycletime(t ck )55.567ns access time (t ac ) 5 5.3 5.5 5.5 ns features jedec standard 3.3v power supply the V54C316162VC is ideally suited for high performance graphics peripheral applications single pulsed ras interface programmable cas latency: 2, 3 all inputs are sampled at the positive going edge of clock programmable wrap sequence: sequential or interleave programmable burst length: 1, 2, 4, 8 and full page for sequential and 1, 2, 4, 8 for interleave udqm & ldqm for byte masking auto & self refresh 2k refresh cycles/32 ms burst read with single write operation description the V54C316162VC is a 16,777,216 bits syn- chronous high data rate dram organized as 2 x 524,288 words by 16 bits. the device is designed to comply with jedec standards set for synchronous dram products, both electrically and mechanically. synchronous design allows precise cycle control with the system clock. the cas latency, burst length and burst sequence must be programmed into device prior to access operation.
2 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 50 pin plastic tsop-ii pin configuration top view pin names v cc i/o 1 i/o 2 v ssq i/o 3 i/o 4 v ccq i/o 5 i/o 6 v ssq i/o 7 i/o 8 v ccq ldqm we cas ras cs ba a 10 a 0 a 1 a 2 a 3 v cc v ss i/o 16 i/o 15 v ssq i/o 14 i/o 13 v ccq i/o 12 i/o 11 v ssq i/o 10 i/o 9 v ccq nc udqm clk cke nc a 9 a 8 a 7 a 6 a 5 a 4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v54c316162v-01 clk clock input cke clock enable cs chip select ras row address strobe cas column address strobe we write enable a 0 ?a 10 address inputs ba bank select i/o 1 ?i/o 16 data input/output ldqm, udqm data mask v cc power (+3.3v) v ss ground v ccq power for i/o?s (+3.3v) v ssq ground for i/o?s nc not connected mosel vitelic V54C316162VC 3 V54C316162VC rev. 1.4 december 2001 block diagram v54c316162v-02 clk cke cs ras cas we dqmi clk address a 0 -a 7 , ba column address buffer row address buffer refresh counter latency 8 burst length output buffer input buffer programming register column decoder sense amplifier timing register column address counter row decoder mux write control logic memory array bank 0 512k x 16 memory array bank 1 512k x 16 row decoder udqm ldqm dqmi i/o 1 -i/o 16 column addresses a 0 -a 10 , ba row addresses column decoder sense amplifier 4 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC signal pin description pin name input function clk clock input system clock input. active on the positive rising edge to sample all inptus cke clock enable activates the clk signal when high and deactivates the clk when low. cke low initiates the power down mode, suspend mode, or the self refresh mode cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and dqmi ras row address strobe latches row addresses on the positive edge of clk with ras low. enables row access & precharge cas column address strobe latches column addresses on the positive edge of clk with cas low. enables column access we write enable enables write operation a 0 -a 10 address during a bank activate command, a 0 -a 10 defines the row address. during a read or write command, a 0 -a 7 defines the column address. in addition to the column address a 10 is used to invoke auto precharge ba define the bank to be precharged. a 10 is low, auto precharge is disabled during a precharge cycle, if a 10 is high, both bank will be precharged , if a 10 is low, the ba is used to decide which bank to precharge. if a 10 is high, all banks will be precharged. ba bank select selects which bank to activate. ba low select bank a and high selects bank b i/o 1 -i/o 16 data input/output data inputs/output are multiplexed on the same pins udqm, ldqm data input/output mask makes data output hi-z. blocks data input when dqm is active vdd/vss power supply/ground power supply. +3.3v 0.3v/ground vddq/vssq data output power/ground provides isolated power/ground to dqs for improved noise immunity nc no connection 5 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC address input for mode set (mode register operation) power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all vcc and vccq pins must be built up simultaneously to the specified voltage when the input signals are held in the ? nop ? state. the power on voltage must not exceed vcc+0.3v on any of the input pins or vcc supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of both banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is di- vided into 4 fields. a burst length field to set the length of the burst, an addressing selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a cas latency field to set the access time at clock cycle and a op- eration mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. the mode set operation must be done before any activate com- mand after the initial power up. any content of the mode register can be altered by re-executing the mode set command. all banks must be in pre- charged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras ,cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. a3 a4 a2 a1 a0 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register cas latency a6 a5 a4 latency 000 reserve 001 reserve 010 2 011 3 101 reserve 110 reserve 111 reserve burst length a2 a1 a0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 full page reserve burst type a3 type 0 sequential 1 interleave test mode a8 a7 mode 00 mode reg set test mode write burst length write burst length a9 length 0burst 1 single bit a10 6 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the select- ed bank is activated and all of sense amplifiers as- sociated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd ,fromthe ras timing. we is used to define either a read (we =h)orawrite(we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 166 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. column address- es are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first ad- dress is ? 2 ? , then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequential burst type and page length is a func- tion of the i/o organisation and column addressing. full page burst operation do not self terminate once the burst length has been reached. in other words, unlike burst length of 2, 4 or 8, full page burst con- tinues until it is terminated using another command. similar to the page mode of conventional dram ? s, burst read or write accesses on any col- umn address are possible once the ras cycle latches the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycles is supported. when the previous burst is interrupted, the remaining ad- dresses are overridden by the new address with the full burst length. an interrupt which accompanies with an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be done between different pages. refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any re- fresh mode. an on-chip address counter increments the word and the bank addresses and no bank infor- mation is required for both refresh modes. burst length and sequence: burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 full page nnn cn, cn+1, cn+2,..... not supported 7 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is re- quired between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self re- fresh mode is available. it enters the mode when ras ,cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high en- ables the clock and initiates the refresh exit opera- tion. after the exit command, at least one t rc delay is required prior to any access command. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ? high ? at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is acti- vated, the write operation at the next clock is prohib- ited (dqm write mask latency t dqw = zero clocks). dqm is used for device selection, byte selection and bus control in a memory system. ldqm con- trols dq0 to dq7, udqm controls dq8 to dq15. suspend mode during normal access mode, cke is held high en- abling the clock. when cke is low, it freezes the in- ternal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver cir- cuits except clk and cke are gated off. the power down mode does not perform any refresh opera- tions, therefore the device can ? t remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by tak- ing cke ? high ? . one clock delay is required for mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, a 10 , to de- termine whether the chip restores or not after the operation. if a 10 is high when a read command is issued, the read with auto-precharge function is initiated. the sdram automatically enters the pre- charge operation one clock before the last data out for cas latencies 2, two clocks for cas latencies 3. if a 10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge op- eration a time delay equal to t wr (write recovery time) after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge op- eration. with a 10 being low, the ba is used select bank to precharge. the precharge command can be imposed one clock before the last data out for cas latency = 2, two clocks before the last data out for cas latency = 3. writes require a time delay twr from the last data out to apply the precharge com- mand. if a 10 is high, all banks will be precharged. burst termination once a burst read or write operation has been ini- tiated, there are several methods in which to termi- nate the burst operation prematurely. these methods include using another read or write com- mand to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop com- mand to terminate the existing burst operation but leave the bank open for future read or write com- mands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid i/o conten- tion. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the i/o pins before the burst stop command is registered will be written to the memory. mosel vitelic V54C316162VC 8 V54C316162VC rev. 1.4 december 2001 absolute maximum ratings* operating temperature range ..................0 to 70 c storage temperature range ............... -55 to 150 c input/output voltage .................. -0.3 to (v cc +0.3) v power supply voltage .......................... -0.3 to 4.6 v power dissipation ............................................. 1 w data out current (short circuit) ...................... 50 ma *note: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operation and characteristics t a =0to70 c; v ss =0v;v cc ,v ccq =3.3v 0.3 v capacitance v dd =3.3v,t a =23 c,f=1mhz,v ref = 1.4v 200mv note: 1. all voltages are referenced to v ss . 2. v ih may overshoot to v cc + 2.0 v for pulse width of < 4ns with 3.3v. v il may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. parameter symbol limit values unit notes min. max. input high voltage v ih 2.0 vcc+0.3 v 1, 2 input low voltage v il ? 0.3 0.8 v 1, 2 output high voltage (i out = ? 2.0 ma) v oh 2.4 ? v output low voltage (i out =2.0ma) v ol ? 0.4 v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 55 a output leakage current (dq is disabled, 0 v < v out 10 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC ac characteristics ( 1,2,3) t a =0to70 c; v ss =0v;v cc =3.3v 0.3 v, t t =1ns # symbol parameter limit values unit -5 -55 -6 -7 min. max. min. max. min. max. min. max. clock and clock enable t ck clock cycle time cas latency = 3 cas latency = 2 5 10 ? ? 5.5 10 ? ? 6 10 ? ? 7 10 ? ? ns ns t ck clock frequency cas latency = 3 cas latency = 2 ? ? 200 100 ? ? 183 100 ? ? 166 100 ? ? 143 100 mhz mhz t ac access time from clock cas latency = 3 cas latency = 2 ? ? 5 7 ? ? 5.3 7 ? ? 5.5 7 ? ? 5.5 7 ns ns 2 3 t ch clock high pulse width 2.5 ? 2.5 ? 2.5 ? 2.5 ? ns t cl clock low pulse width 2.5 ? 2.5 ? 2.5 ? 2.5 ? ns t t transitiontime 110110110110ns setup and hold times t cmds command setup time 2 ? 2 ? 2 ? 2 ? ns 4 t as address setup time 2 ? 2 ? 2 ? 2 ? ns 4 t ds data in setup time 2 ? 2 ? 2 ? 2 ? ns 4 t cks cke setup time 2 ? 2 ? 2 ? 2 ? ns 4 t cmdh command hold time 1 ? 1 ? 1 ? 1 ? ns 4 t ah address hold time 1 ? 1 ? 1 ? 1 ? ns 4 t dh data in hold time 1 ? 1 ? 1 ? 1 ? ns 4 t ckh cke hold time 1 ? 1 ? 1 ? 1 ? ns 4 common parameters t rcd row to column delay time 15 ? 16.5 ? 18 ? 18 ? ns 5 t ras rowactivetime 40100k45100k48100k48100k ns 5 t rc row cycle time 60 ? 63 ? 66 ? 70 ? ns 5 t rp row precharge time 15 ? 17 ? 18 ? 21 ? ns 5 t rrd activate(a) to activate(b) com- mand period 10 ? 11 ? 12 ? 14 ? ns 5 t ccd cas (a) to cas (b) command pe- riod 1 ? 1 ? 1 ? 1 ? clk t rcs mode register set-up time 10 ? 11 ? 12 ? 14 ? ns t sb powerdownmodeentrytime0505.50607ns t cdl last data in to new column ad- dress delay 5 ? 5.5 ? 6 ? 7 ? ns 11 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC t bdl last data in to burst stop 5 ? 5.5 ? 6 ? 7 ? ns refresh cycle t ref refresh period (2048 cycles) ? 32 ? 32 ? 32 ? 32 ms t srex self refresh exit time 2 clk + t rc 2clk+t rc 6 read cycle t oh data out hold time 2.5 ? 2.5 ? 2.5 ? 2.5 ? ns t hz cas latency = 3 cas latency = 2 ? ? 5 7 ? ? 5.3 7 ? ? 5.5 7 ? ? 5.5 7 ns t dqz dqm data out disable latency 2 ? 2 ? 2 ? 2 ? clk t lz data out low-z time ? 1 ? 1 ? 1 ? 1ns write cycle t wr write recovery time cas latency = 3 cas latency = 2 5 10 ? ? 5.5 10 ? ? 6 10 ? ? 7 10 ? ? ns ns t dqw dqm write mask latency 0 ? 0 ? 0 ? 0 ? clk t rdl last data in to row precharge 10 ? 11 ? 12 ? 14 ? ns ac characteristics ( 1,2,3) (continued) t a =0to70 c; v ss =0v;v cc =3.3v 0.3 v, t t =1ns # symbol parameter limit values unit -5 -55 -6 -7 min. max. min. max. min. max. min. max. 12 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 1.for proper power-up see the operation section of this data sheet. 2.ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1ns with the ac output load circuit shown in figure 1 notes for ac parameters: 1.4v 1.4v tcs tch tac tac tlz toh thz clk command output 50 pf i/o z=50 ohm +1.4v 50 ohm vih vil t t figure 1. tck 3.if clock rising time is longer than 1 ns, a time (t t /2 ? 0.5) ns has to be added to this parameter. 4.if t t islongerthan1ns,atime(t t ? 1) ns has to be added to this parameter. 5.these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6.self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 13 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1readtowriteinterval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 5.1 burst write to precharge 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst write & read with auto-precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge 8. burst termination 8.1 termination of a full page burst write operation 8.2 termination of a full page burst write operation 14 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 1. bank activate command cycle (cas latency = 3) 2. burst read operation (burst length = 4, cas latency = 2, 3) address clk t0 t t1 t ttt command nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate t rcd : ? h ? or ? l ? t rc precharge t rrd bank b row addr. command read a nop nop nop nop nop nop nop dout a 0 cas latency = 2 t ck3, i/o ? s cas latency = 3 dout a 1 dout a 2 dout a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck2, i/o ? s dout a 0 dout a 1 dout a 2 dout a 3 15 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 3. read interrupted by a read (burst length = 4, cas latency = 2, 3) 4.1 read to write interval (burst length = 4, cas latency = 3) command read a read b nop nop nop nop nop nop t ck2, i/o ? s cas latency = 2 t ck3, i/o ? s cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 command nop read a nop nop nop nop write b nop nop dqm dout a 0 din b 0 din b 1 din b 2 must be hi-z before the write command i/o ? s minimum delay between the read and write commands = 4+1 = 5 cycles clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t dqz t dqw : ? h ? or ? l ? 16 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 4.2 minimum read to write interval (burst length = 4, cas latency = 2) 4.3 non-minimum read to write interval (burst length = 4, cas latency = 2, 3 command nop bank a nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 must be hi-z before the write command t ck2, i/o ? s cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop activate 1 clk interval t dqz t dqw : ? h ? or ? l ? nop read a nop nop read a nop write b nop nop dqm din b 0 din b 1 din b 2 t ck1, i/o ? s cas latency = 2 t ck2, i/o ? s cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 command din b 0 din b 1 din b 2 dout a 1 dout a 0 must be hi-z before the write command t dqz t dqw : ? h ? or ? l ? 17 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 5. burst write operation (burst length = 4, cas latency = 2, 3) 6.1 write interrupted by a write (burst length = 4, cas latency = 2, 3) command nop write a nop nop nop nop nop nop i/o ? s din a 0 din a 1 din a 2 din a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is ignored after the first data element and the write are registered on the same clock edge. termination of a burst. don ? t care command nop write a write b nop nop nop nop nop i/o ? s din a 0 din b 0 din b 1 din b 2 nop din b 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 tcdl t0 t2 t1 t3 t4 t5 t6 t7 t8 clk command nop write nop nop nop nop pre nop nop din a 0 din a 1 din a 2 din a 3 i/o ? s trdl 5.1 write to precharge 18 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 6.2 write interrupted by a read (burst length = 4, cas latency = 2, 3) 7. burst write with auto-precharge burst length = 2, cas latency = 2, 3) command nop write a read b nop nop nop nop nop nop t ck2, i/o ? s cas latency = 2 din a 0 t ck3, i/o ? s cas latency = 3 din a 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 don ? t care don ? t care don ? t care dout b 0 dout b 1 dout b 2 input data must be removed from the i/o ? s at least one clock cycle before the read dataappears on the outputs to avoid data contention. command nop nop nop write a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop bank a active nop nop din a 0 din a 1 * i/o ? s cas latency = 3 begin autoprecharge bank can be reactivated after trp * t wr t rp din a 0 din a 1 t wr t rp nop * i/o ? s cas latency = 2 19 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 7.2 burst read with auto-precharge burst length = 4, cas latency = 2, 3) command read a nop nop nop nop nop nop nop nop t ck2, i/o ? s cas latency = 2 t ck3, i/o ? s cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 3 dout a t rp t rp * * * * 0 dout a 1 dout a 2 dout a 3 dout a begin autoprecharge bank can be reactivated after t rp 0 dout a 1 dout a 2 20 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC 8.1 termination of a full page burst read operation (cas latency = 2, 3) 8.2 termination of a full page burst write operation (cas latency = 2, 3) command read a nop nop nop burst nop nop nop nop t ck2, i/o ? s cas latency = 2 t ck3, i/o ? s cas latency = 3 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 the burst ends after a delay equal to the cas latency. dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 command nop write a nop nop burst nop nop nop nop din a 0 din a 1 din a 2 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. i/o ? s cas latency = 2,3 don ? t care tbdl 21 V54C316162VC rev. 1.4 december 2001 mosel vitelic V54C316162VC package diagram 50-pin plastic tsop-ii (400 mil) 50 26 125 0.016 +0.002 ? 0.004 0.4 +0.05 ? 0.1 0.006 +0.003 ? 0.001 0.15 +0.08 ? 0.03 0.008 [0.2] 44x m unit in inches [mm] 0.004 0.002 [0.1 0.05] 0.031 [0.8] 0.039 0.002 [1 0.05] 0.4 0.005 [10.16 0.13] 0.463 0.008 [11.76 0.2] 0.047 max [1.2 max] 0.004 [0.1] 0.825 0.005 [20.95 0.13] does not include plastic or metal protrusion of 0.010 [0.25] max. per side 1 1 0.020 0.004 [0.5 0.1] mosel vitelic worldwide offices V54C316162VC ? copyright, mosel vitelic inc. printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-352-3775 fax: 214-904-9029 |
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